ïÔ: D&R SoC NewsAlert [SoC-NewsAlert@design-reuse.com]
ïÔÐÒÁ×ÌÅÎÏ: 7 ÄÅËÁÂÒÑ 2004 Ç. 13:57
ëÏÍÕ: Michael Dolinsky
ôÅÍÁ: D&R SoC News Alert - December 7, 2004
DR SoC News Alert
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December 7, 2004    


Michael,
Welcome to issue of December 7, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: IP/SOC 2004

We expect to see all of you at IP/SOC 2004 conference and exhibition (Dec.8-9, 2004 - Grenoble, France) the worldwide unique and hottest event dedicated to IP based SoC design. Not only you will get the most advanced technical views, the highly qualified visions in the field but you also be able to attend the most fascinating panel discussions.

Register now.

Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core from Eureka Technology
SSL/TLS record processing engine for gateway applications from Elliptic Semiconductor
HyperTransport e Verification Component (eVC) from HDL Design House
Serial ATA Controller Core from StellarIP Solutions
20-bit, 93dB Dynamic Range, 16 to 48kHz Sampling, 1.8 to 3.6V Supply, Stereo Audio ADC from ChipIdea Microelectronics
Flash & EEPROM IP from Flasys Corp.
Wanted IPs :
  • 10/100 Ethernet PHY
  • MDDI type-1 digital controller
  • Platform MCUs Give Maximum Return
    Migration path laid to low-cost 32-bit MCUs
    The why, where and what of low-power SoC design
    8-bit microcontrollers: still going . . .
    Semiconductor options for real-time signal processing
    IP/SOC PRODUCTS
    QualCore Logic Adds Serial ATA, SerDes Cores to Product Portfolio
    Synopsys Announces Industry's First Fully Released Verification IP for the AMBA 3 AXI Standard
    Agere Systems Announces New Serial Platform for Universal Support of High-Speed Interface Standards
    Eureka Technology simplifies memory system design with high performance MemConnect solution
    EEMBC and Patriot Scientific Announce Benchmark Scores for IGNITE™ 2FX Processor
    Agilent Technologies Proves High-Performance 6.25 Gb/s SerDes Core in 90-Nanometer CMOS Process
    NewLogic Offers WLAN 802.11h Implementation with Enhanced Radar Detection
    Chipcon reveals launch plans for the industry's first All-In-One IEEE 802.15.4/ZigBee System-On-Chip solution
    DEALS
    MIPS Technologies Licenses Highest-Performance, MIPS32 24K Core Family to Micronas
    Transmeta Licenses Advanced Power Management and Transistor Leakage Control Technologies to Fujitsu
    Altera Uses Verisity's Plug-and-Play Components to Speed Verification of its Intellectual Property
    Datang Expands Its ZSP Cores Licensing Agreement with LSI Logic for Use in 3G Wireless Applications
    Shengyang Institute of Automation Licenses ARM Processor For Advanced Automation Research
    BUSINESS
    Conexant Expands Product Development Resources in India; Paxonet Acquisition Adds More Than 100 Experienced Design Engineers
    ARM and Artisan Confirm Average Share Price Measurement Period
    DESIGN SERVICES
    QualCore Logic Builds Strong Analog Design Team in India and California
    eInfochips selected to operate QLogic Design Center
    EMBEDDED SYSTEMS
    Enea introduces embedded software platform for automobiles
    Accelerated Technology Announces USB On-The-Go Support Now Available for Embedded Developers Using the Nucleus RTOS
    FOUNDRIES
    Chartered Strengthens 0.13-Micron and 0.18-Micron Solutions with Enhanced Design Services Alliance Program
    Silterra Demonstrates Functional 0.13-Micron SRAM
    FPGA/CPLD
    Actel Introduces Enhanced Low-Cost Starter Kit for Flash-Based FPGAs
    Altera's Quartus II Version 4.2 Delivers FPGA and CPLD Performance Leadership
    FABLESS
    FSA Reports 30 Percent YoY Worldwide Fabless Revenue Growth in Q3 2004
    OTHER
    Falanx Technology to Drive 3D Graphics for Smartphones based on Symbian OS

    SPONSORED BY: TEMENTO SYSTEMS

    Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

    Click here to know more about Temento


    IP/SOC 2004
    Grenoble, France
    December 8-9, 2004


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    D&R Verification IP Catalog :
    Speed up your verification of protocol-centric designs by finding the specific Verification IP you need (already more than 100 products listed !!!)



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